1. Technical Field
This invention relates in general to semiconductor memory devices and to their operation, and more particularly, to dynamic random access memory (DRAM) devices configured with a novel open bit line architecture and to an operational method thereof.
2. Background Art
Architecture of semiconductor memories is roughly divided into two types, namely, open bit line architecture and folded bit line architecture. Both architecture types are well known in the art and detailed information on each type, along with numerous variations thereon, is readily available in the open literature. (The present invention comprises a novel variation on a conventional open bit line architecture.)
In comparison with folded bit line architecture, open bit line architecture is more suitable for very close packing of memory cell arrays. Notwithstanding this, product chips using conventional open bit line cell arrays are rarely implemented, primarily because common mode noise reduction inherent in folded bit line architecture is lacking in open bit line architecture, at least without significant additional process complexity, signal loss and/or performance degradation. In view of the continuing advancement in the art towards greater and greater circuit integration, the open bit line configuration is drawing significant attention throughout the memory industry, especially in relation to 16 Mbit, 64 Mbit, and beyond, memories. This is because an open bit line architecture provides a memory cell at every X,Y cross-point location of the array, which is not possible with folded bit line architecture.
Folded bit line architecture (commonly used in DRAMs of, for example, 256 Kbits or 1 Mbits) is inherently limited by the degree of integration obtainable within a defined area. Since a folded memory array cannot accommodate disposition of a memory cell at each bit line, word line intersection (i.e., cross-point), the configuration is by necessity less dense than an open bit line memory structure. By way of example, folded bit line architecture typically requires twenty-five percent, or more, area than open bit line architecture to implement the same size memory array. Thus, in terms of density of structure, an open bit line configuration clearly has the advantage. However, common mode noise difficulties inherent in conventional open bit line architectures have limited its commercial manufacture.
In addition to inherent common mode noise imbalance, another difficulty experienced with conventional open bit line architectures is the problem of dealing with the reference bit line. The reference bit line, which in a folded architecture supplies common-mode noise rejection, is for open bit line architecture either a parasitic capacitance liability or a source of additional noise.
Thus, a genuine need exists in the semiconductor memory art for a more stable, less complex memory device which has the performance characteristics of a conventional folded bit line memory device, but yet has the cell density of open bit line architecture.